1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device that is provided with a polycide interconnection layer having a silicide film formed on a polycrystal silicon film, and a method for fabricating the semiconductor device.
2. Description of the Related Art
Conventionally, polycrystal silicon that is an electrically conductive material durable against high heat treatments has been widely used as a material of various kinds of wiring layers. A gate electrode of a MOS transistor represents one of the wiring layers. However, even if impurities are introduced or admitted to the polycrystal silicon film by as much an amount as possible in order to increase the conductivity of the polycrystal silicon film, there arises a problem that the resulting resistivity is very higher than that of a film of metal such as aluminum. To solve this problem, a polycide inter-connection layer that is chemically stable and has low resistivity is widely used for the wiring layer. The polycide interconnection layer is formed by the following way. A high melting-point metal film is formed on the polycrystal silicon film. Then, the two films are caused to undergo a solid state reaction through a heat treatment, so that a silicide film is formed. The high melting-point metal film includes a metal selected from tungsten, titanium, tantalum, ruthenium, zirconium, molybdenum and cobalt, for example.
However, when the polycide interconnection layer, especially, a polycide gate electrode is formed, the following problems face. The heat treatment is applied after ion-implanting the impurities into the polycrystal silicon film formed on a gate insulating film and forming the high melting-point metal film. As the solid state reaction of the polycrystal silicon film with the high melting-point metal film proceeds at a low rate, the heat treatment must be conducted for a long time. Accordingly, if the solid state reaction rate is irregular or uneven, the reaction rate in the direction toward the gate insulating film becomes non-uniform. As a result, the tip portions of the silicide film reach the gate insulating film, so that it leads to a problem that disadvantages such as the generation of leak current and the decrease in breakdown voltage are sometimes caused.
As one solution to this problem, the following method is disclosed in JP-A-62-55928. A second polycrystal silicon film not doped with impurities (non-doped polycrystal silicon film) is formed on a first polycrystal silicon film doped with impurities (phosphorus). A high melting-point metal film (titanium film) is formed on the second polycrystal silicon film, and then the reaction for forming silicide is carried out. According to this method, the first polycrystal silicon film plays the role of a stopper when the solid state reaction proceeds, so that the solid state reaction can be prevented from reaching the gate insulating film. In this method, however, the polycrystal silicon film of a two-layer structure having the doped first polycrystal silicon film and the non-doped second polycrystal silicon film must be formed. As a result, the number of fabrication steps is necessarily increased and the structure is necessarily complicated, so that it is possibly an obstacle to the formation of a semiconductor device with high density and high integration demanded in recent years.
The following JP-A-6-326304 and JP-A-7-263686 disclose methods for forming the polycide interconnection layer.
(1) JP-A-6-326304
This publication discloses the following method in order to prevent a gate electrode from suffering damage by suppressing stress exerting on a gate oxide film when the gate electrode of polycide structure is formed. A phosphorus doped amorphous silicon film is formed. The phosphorus doped amorphous silicon film is converted into a phosphorus doped polysilicon film by a heat treatment which is applied at a temperature which is lower than a maximum temperature in a heat treatment process for forming source and drain regions. A tungsten silicide film is formed on the phosphorus doped polysilicon film, and then the two films are patterned to form the gate electrode.
(2) JP-A-7-263686
This publication discloses the following method in order to prevent abnormal oxidization of a polycide interconnection layer surface and peel-off of a high melting-point silicide film and in order to prevent the high melting-point metal silicide film and polysilicon film from being left behind in patterning for forming a gate electrode wiring. A polysilicon film and a tungsten silicide film are sequentially formed on a gate oxide film. The polysilicon film and the tungsten silicide film are patterned to form a gate electrode wiring. A thin oxide film is formed on the tungsten silicide film.
An object of the present invention is to provide a semiconductor device in which the increase in the number of fabrication steps and the complication of the structure can be prevented, the control of the heat treatment for forming silicide can be facilitated, and the resistivity of conductive layers can be decreased during mass production to increase the operation speed of the semiconductor device, and to provide a method for fabricating the semiconductor device.
A first semiconductor device according to the present invention comprises: a semiconductor substrate; and a conductive layer formed above the semiconductor substrate, wherein the conductive layer includes: a silicon film including a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities; a silicide film formed on the impurity layer of the silicon film; and a high melting point metal film formed on the silicide film.
A second semiconductor device according to the present invention comprises: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; and a conductive layer formed on the insulating layer, wherein the conductive layer includes: a silicon film including a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities; a silicide film formed on the impurity layer of the silicon film; and a high melting-point metal film formed on the silicide film.
A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device having a semiconductor substrate and a conductive layer formed above the semiconductor substrate, and comprises a step of forming the conductive layer. In the method, the step of forming the conductive layer comprises: a first step of forming a non-doped silicon film above the semiconductor substrate; a second step of introducing impurities the non-doped silicon film so as to form an impurity layer, which contains the impurities, at only an inner intermediate portion of the non-doped silicon film; a third step of forming a high melting-point metal film on the non-doped silicon film having the impurity layer at only the inner intermediate portion; and a fourth step of reacting the non-doped silicon film having the impurity layer at only the inner intermediate portion with the high melting-point metal film through a heat treatment to form a silicide film at an interface and near the interface between the high melting-point metal and the non-doped silicon film having the impurity layer at only the inner intermediate portion.
In the present invention, the silicon film (for example, a polycrystal silicon film or an amorphous silicon film) is formed on an insulating film (for example, a gate insulating film or an interlayer insulating film). The impurities are introduced to the silicon film in such a manner that the impurities do not reach the insulating film. Subsequently, the high melting-point metal film is formed on the silicon film, and then the two films are caused to undergo the solid state reaction to form a silicide film near the interface between the two films. At that time, the lower the concentration of the impurities introduced to the silicon film, the higher the rate of the solid state reaction of the silicon film with the high melting-point metal film becomes. In other words, a non-doped silicon film and a silicon film having a high impurity concentration level are taken, the solid state reaction rate is drastically higher for the former than for the latter. Accordingly, when the impurity concentration profile of the impurity layer is made to be very steep at the interface between the impurity layer and the high melting-point metal film by introducing the impurities to only an inner intermediate portion of the silicon film to form the impurity layer only at the inner intermediate portion of the silicon film, the impurity layer can be used as a stopper against the solid state reaction. As a result, even when the rate of the solid state reaction of the silicon film with the high melting-point metal film becomes irregular, the solid state reaction rate is abruptly decreased at the impurity layer, thus preventing the solid state reaction from being so affected by the irregularity as to reach the insulating film. Through this, a conductive layer (for example, a polycide layer) substantially meeting an intended design can be formed.